Описание интерфейса D-триггера

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Национальный исследовательский университет

Московский энергетический институт

Институт автоматики и вычислительной техники

Кафедра вычислительных машин, систем и сетей

Лабораторная работа

по курсу

"Современные методы проектирования цифровых устройств"

Выполнил студент

группы А-07м-16

Сафоненко Даниил

Москва, 2016



Описание интерфейса D-триггера

library IEEE;-- используется стандартная библиотека IEEE

use IEEE.STD_LOGIC_1164.ALL;-- подключаемые пакеты

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;--ниже закомментированы

неиспользуемые

---- Uncomment the following library declaration if instantiating

---- any XILINX primitives in this code.

---- library UNISIM;

---- use UNISIM.VComponents.all;

----- Описание объекта проекта dff-----------------------------------------

entity dff is -- объект проекта D- триггер - описание его интерфейса

Port ( d : in std_logic;

clk : in std_logic;

q : out std_logic);

end dff;

architecture Behavioral of dff is -- поведенческое описание D- триггера

begin

process (clk)

begin

if ( clk='1' and clk'event) then

q<=d;

end if;

end process;

end Behavioral;



Тестовая программа

Описание тестирующей программы может быть в отдельном файле, а для его автоматизированного получения можно использовать средства САПР ISE.

LIBRARY ieee; -подключение стандартных библиотек и пакетов

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY dff_test_bench IS --описание интерфейса теста dff_test_bench

END dff_test_bench;

ARCHITECTURE behavior OF dff_test_bench IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT dff

PORT(d : IN std_logic; clk : IN std_logic; q : OUT std_logic);

END COMPONENT;

--Inputs-входы, язык VHDL не различает прописные и строчные буквы

SIGNAL d : std_logic := '0';-- в именах и ключевых словах

SIGNAL clk : std_logic := '0';

--Outputs-выходы

SIGNAL q : std_logic;

BEGIN -- инсталяция тестируемого объекта-Instantiate the Unit Under

Test (UUT)

uut: dff PORT MAP(d => d, clk => clk, q => q );

-------------Тест сделан с учетом возможности не только поведенческого,

-------------но и пост-синтезного моделирования

gen: process --- процесс- генератор тактов - период 20 ns

begin

clk<='0';wait for 20 ns;

clk <= '1';wait for 20 ns;

end process;

test: process

begin

wait for 100ns;

wait until clk'event and clk='0'; d<='0';

wait until clk'event and clk='0'; d<='1';

wait until clk'event and clk='0'; d<='0';

end process;

-- процесс сравнения выходов тестируемого объекта с ожидаемыми

check: process -- процесс самопроверки

begin

wait until clk'event and clk='1';

wait for 19 ns;-- задержка на предполагаемое время прохождения

---сигнала в D-триггере и выходном порте микросхемы!

assert(d = q) report "OCHIBKA !! MISCOMPARING ERROR"

severity FAILURE;

end process;

end;

Synthesis report

Release 14.7 - xst P.20131013 (nt64)

Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

--> Parameter TMPDIR set to xst/projnav.tmp

Total REAL time to Xst completion: 0.00 secs

Total CPU time to Xst completion: 0.06 secs

--> Parameter xsthdpdir set to xst

Total REAL time to Xst completion: 0.00 secs

Total CPU time to Xst completion: 0.06 secs

--> Reading design: dff.prj

TABLE OF CONTENTS

1) Synthesis Options Summary

2) HDL Compilation

3) Design Hierarchy Analysis

4) HDL Analysis

5) HDL Synthesis

5.1) HDL Synthesis Report

6) Advanced HDL Synthesis

6.1) Advanced HDL Synthesis Report

7) Low Level Synthesis

8) Partition Report

9) Final Report

9.1) Device utilization summary

9.2) Partition Resource Summary

9.3) TIMING REPORT

* Synthesis Options Summary *

---- Source Parameters

Input File Name : "dff.prj"

Input Format : mixed

Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "dff"

Output Format : NGC

Target Device : xc3s50-5-pq208

---- Source Options

Top Module Name : dff

Automatic FSM Extraction : YES

FSM Encoding Algorithm : Auto

Safe Implementation : No

FSM Style : LUT

RAM Extraction : Yes

RAM Style : Auto

ROM Extraction : Yes

Mux Style : Auto

Decoder Extraction : YES

Priority Encoder Extraction : Yes

Shift Register Extraction : YES

Logical Shifter Extraction : YES

XOR Collapsing : YES

ROM Style : Auto

Mux Extraction : Yes

Resource Sharing : YES

Asynchronous To Synchronous : NO

Multiplier Style : Auto

Automatic Register Balancing : No

---- Target Options

Add IO Buffers : YES

Global Maximum Fanout : 500

Add Generic Clock Buffer(BUFG) : 8

Register Duplication : YES

Slice Packing : YES

Optimize Instantiated Primitives : NO

Use Clock Enable : Yes

Use Synchronous Set : Yes

Use Synchronous Reset : Yes

Pack IO Registers into IOBs : Auto

Equivalent register Removal : YES

---- General Options

Optimization Goal : Speed

Optimization Effort : 1

Keep Hierarchy : No

Netlist Hierarchy : As_Optimized

RTL Output : Yes

Global Optimization : AllClockNets

Read Cores : YES

Write Timing Constraints : NO

Cross Clock Analysis : NO

Hierarchy Separator : /

Bus Delimiter : <>

Case Specifier : Maintain

Slice Utilization Ratio : 100

BRAM Utilization Ratio : 100

Verilog 2001 : YES

Auto BRAM Packing : NO

Slice Utilization Ratio Delta : 5

* HDL Compilation *

Compiling vhdl file "C:/Users/Sofon/Desktop/dff.vhd" in Library work.

Entity <dff> compiled.

Entity <dff> (Architecture <Behavioral>) compiled.

* Design Hierarchy Analysis *

Analyzing hierarchy for entity <dff> in library <work> (architecture

<Behavioral>).

* HDL Analysis *

Analyzing Entity <dff> in library <work> (Architecture <Behavioral>).

Entity <dff> analyzed. Unit <dff> generated.

* HDL Synthesis *

Performing bidirectional port resolution...

Synthesizing Unit <dff>.

Related source file is "C:/Users/Sofon/Desktop/dff.vhd".

Found 1-bit register for signal <q>.

Summary:

inferred 1 D-type flip-flop(s).

Unit <dff> synthesized.

HDL Synthesis Report

цифровой автоматизированный тестирующий триггер

Macro Statistics

# Registers : 1

1-bit register : 1

* Advanced HDL Synthesis *

Advanced HDL Synthesis Report



Macro Statistics

# Registers : 1

Flip-Flops : 1

* Low Level Synthesis *

Optimizing unit <dff> ...

Mapping all equations...

Building and optimizing final netlist ...

Found area constraint ratio of 100 (+ 5) on block dff, actual ratio is 0.

Final Macro Processing ...

Final Register Report

Macro Statistics

# Registers : 1

Flip-Flops : 1

* Partition Report *

Partition Implementation Status

No Partitions were found in this design.

Final Results

RTL Top Level Output File Name : dff.ngr

Top Level Output File Name : dff

Output Format : NGC

Optimization Goal : Speed

Keep Hierarchy : No

Design Statistics

# IOs : 3

Cell Usage :

# FlipFlops/Latches : 1

# FD : 1

# Clock Buffers : 1

# BUFGP : 1

# IO Buffers : 2

# IBUF : 1

# OBUF : 1

Device utilization summary:

Selected Device : 3s50pq208-5

Number of Slices: 0 out of 768 0%

Number of IOs: 3

Number of bonded IOBs: 3 out of 124 2%

IOB Flip Flops: 1

Number of GCLKs: 1 out of 8 12%

Partition Resource Summary:

No Partitions were found in this design.



TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS

ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE

TRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.

Описание D-триггера

Описание тестирующей программы может быть в отдельном файле, а для его автоматизированного получения можно использовать средства САПР ISE.

Clock Information:

------------------

-----------------------------------+------------------------+-------+

Clock Signal | Clock buffer(FF name) | Load |

-----------------------------------+------------------------+-------+

clk | BUFGP | 1 |

-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:

----------------------------------------

No asynchronous control signals found in this design

Timing Summary:

---------------

Speed Grade: -5



Minimum period: No path found

Minimum input arrival time before clock: 1.572ns

Maximum output required time after clock: 6.216ns

Maximum combinational path delay: No path found

Timing Detail:

--------------

All values displayed in nanoseconds (ns)

Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'

Total number of paths / destination ports: 1 / 1

-------------------------------------------------------------------------

Offset: 1.572ns (Levels of Logic = 1)

Source: d (PAD)

Destination: q (FF)

Destination Clock: clk rising

Data Path: d to q

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

IBUF:I->O 1 0.715 0.681 d_IBUF (d_IBUF)

FD:D 0.176 q

----------------------------------------

Total 1.572ns (0.891ns logic, 0.681ns route)

(56.7% logic, 43.3% route)

Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'

Total number of paths / destination ports: 1 / 1



Offset: 6.216ns (Levels of Logic = 1)

Source: q (FF)

Destination: q (PAD)

Source Clock: clk rising

Data Path: q to q

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FD:C->Q 1 0.626 0.681 q (q_OBUF)

OBUF:I->O 4.909 q_OBUF (q)

----------------------------------------

Total 6.216ns (5.535ns logic, 0.681ns route)

(89.0% logic, 11.0% route)

Total REAL time to Xst completion: 4.00 secs

Total CPU time to Xst completion: 3.79 secs

-->

Total memory usage is 255560 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 0 ( 0 filtered)

Number of infos : 0 ( 0 filtered)

PlanAhead

NET "clk" LOC = T9;

NET "d" LOC = L14;

NET "q" LOC = P11;

Technology схема

RTL схема

Временная диаграмма

Временная диаграмма Post-Route

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